1. Field of the Invention
The present invention relates to a ferroelectric memory device and, more specifically, to a ferroelectric memory device having a folded bit line architecture.
2. Description of the Related Art
Ferroelectric memory devices are generally well known in the data processing arts. Ferroelectric memories use ferroelectric capacitors for data storage. The ferroelectric capacitor is desirable because it may retain an electric field developed therein, even after a voltage applied to the capacitor to develop the field is removed. Therefore, ferroelectric memory cells do not require refreshing to retain a field stored therein.
A plurality of ferroelectric memory devices may be incorporated into a ferroelectric memory array. The memory array may be comprised of a plurality of word line rows, a plurality of plate line rows, and a plurality of bit line columns. Typically, memory cells and reference cells are attached to bit line columns, and these memory cells and reference cells are activated via signals on word line rows and the plate line rows provide the signals to be placed into memory. A memory cell may include a ferroelectric capacitor and an access transistor connecting it to a bit line. A reference cell may include a pair of oppositely charged ferroelectric capacitors and a pair of access transistors connecting these ferroelectric capacitors to a bit line.
One known architecture for the formation of a ferroelectric memory array is an open bit line architecture. In an open bit line architecture, a plurality of memory cells may be placed on a single bit line. This architecture permits a high component density. However, this architecture is also susceptible to electrical noise.
Another known architecture for the formation of a ferroelectric memory array is a folded bit line architecture. This architecture is not as susceptible to electrical noise as is the open bit line architecture, as the close spacing of cells in a folded bit line architecture provides good common mode rejection. However, the component density is somewhat less than for open bit line architecture. The present invention is directed to a folded bit line architecture.